1. Field of the Invention
This invention relates to a redundant system of a plesiochronous matching apparatus for correcting a difference between the transmitting speeds of two digital signal systems transmitting and receiving a signal therebetween, the two digital signal systems having clock frequencies of accuracy within the range of .+-.1.times.10.sup.-11, as defined in the Recommendation G.8111 of the Comite Consultatif International Telegraphique et Telephonique (CCITT).
2. Description of the Prior Art
A plesiochronous matching apparatus corrects, as described above, a difference between the transmitting speeds of two digital signal systems having an extremely small difference in the permissible clock frequencies. For this purpose, this apparatus matches the data transmitting speeds of the two systems by reading and discarding or reading twice a digital data signal corresponding to a given period of time when the total of the difference of the transmission bits of the two systems attains a predetermined value.
FIG. 1 illustrates a concept of a plesiochronous matching apparatus. As shown, a plesiochronous matching apparatus is compared imaginarily to a memory having the shape of a ring. An input signal is written in this memory as write data, while read data is taken out from the memory as an output signal. In FIG. 1, the ring shaped memory has the total number N of addresses from the address 0 to the address N-1. In the state shown, an input signal is written in the address W as write data and an output signal is read out from the address R as read data. In FIG. 1, the writing order and the reading order respectively proceeds clockwise.
When the data transmitting speed of the system on the input side is equal to the data transmitting speed of the system on the output side, a fixed distance is maintained in the relative positional relation between a write address and a read address in any position of the ring shaped memory. As a result, data is read out always from the address coming afterwards by W-R addresses from the write address.
However, if there is a difference between the data transmitting speed of the system on the input side and that of the system on the output side, the relative distance between a related write address and a related read address changes as the time proceeds. If the data transmitting speed on the input side is faster than that on the output side, a write address approaches and finally overtakes a read address. On the contrary, if the speed on the input side is slower than that on the output side, a read address approaches and finally overtakes a write address.
Let us consider this phenomenon with regard to the addresses on the read side. If the data transmitting speed of the system on the input side is faster than that of the system on the output side, advance is made along the write addresses as the time proceeds and a write address approaches a read address clockwise. On the contrary, if the data transmitting speed of the system on the input side is slower than that of the system on the output side, delay is made along the write addresses as the time proceeds and a write address approaches a read address counterclockwise. The distance between a write address and a read address decreases according to the passage of the time and if the operation is left continuing, a write address and a read address will coincide with each other and finally a write address will get ahead of a read address. This means that the data for one round of a ring buffer is read and discarded in case where the write speed is relatively faster than the read speed. This means also that in case where the read speed is relatively faster on the contrary, the data already read corresponding to one cycle of a ring buffer is read out again.
Since there is a difference between the data transmitting speed on the input side and that on the output side, discarding or rereading of data in any form cannot be avoided. However, if there is no regularity in the range of the data discarded or reread, much inconvenience is caused in signal processing. Therefore, a plesiochronous matching apparatus provides a control operation so that a unit for discarding or rereading data may be a fixed unit defined according to predetermined regularity.
As the fixed unit, a unit having fixed periodical characteristic such as a sample unit, a frame unit or a multiframe unit in a digital signal for PCM telephone line is commonly selected.
Referring to FIG. 1, it is assumed for example that the unit for slip control for discarding or rereading is equal to the data for J addresses corresponding to the data for one frame, and that the threshold for detecting the approach of write and read addresses for slipping of data is equal to a difference of 2 addresses. It is also assumed that the write speed is faster than the read speed and that the write address approaches the read address clockwise.
Now, let us consider that the write address approaches the address R-3 when the read address is at the last address R-1 of a certain frame and is only two addresses ahead of the write address. Although the read address advances normally to the address R, slip control is made in this case so that the read address advances to the address R-J one frame ahead. Further, the case where the write speed is slower than the read speed and the write address approaches the read address counterclockwise will be considered. Now, let us assume that when the read address comes to the last address R+J-1 of a certain frame, the write address is still at the address R+J+1 which is ahead of it by two addresses. Normally, the read address would advance to the address R+1. However, in this case, slip control is effected so that the read address is returned to the address R which is the first address of the initial frame.
Thus, when the write or read address comes within a predetermined range as one another, slip control is regularly made for each predetermined gap of divided data so that a predetermined amount of data is discarded or reread and matching is applied to the slightly different data transmitting speeds of the two digital signal systems. In such a manner, operation of a plesiochronous matching apparatus is generally performed.
The accuracy of the clock frequencies of the two systems performing plesiochronous matching operation varies within a permissible range and there is a fear that the relative relation between the clock frequencies of the two systems established till then may be completely reversed at the moment certain slip control is made. In order to apply effectively the matching in the worst condition as described above, it is necessary to maintain the minimum time period for slip control at more than a fixed value. More specifically, it is necessary that the difference between the write address and the read address after application of slip control should be more than the slip amount, for example, more than the amount for one frame measured in either of the clockwise and counterclockwise directions. Accordingly, by taking account of the write and read addresses, the capacity of a matching buffer memory needs to be more than the number of addresses for two frames plus one address.
If the threshold value for detection of a difference of the addresses is set at a point more distant than the adjacent address for the purpose of safety, it is necessary to further increase a memory capacity. In addition, it is difficult in the slip control to apply slipping from an arbitrary address to an address distant therefrom by one frame by counting a difference of the addresses. Therefore, the capacity of a matching buffer memory is selected to be an integer multiple of the frame capacity exceeding two frames if slip control is to be made for a frame unit. Further, an address fixing and allocating method in which the respective addresses of a matching buffer receive fixed bits of each frame unit data is adopted so that the respective gaps of the slip units always exist in fixed addresses regularly positioned, in a control buffer memory, which makes it easy to provide slip control.
Now, a conventional plesiochronous matching apparatus performing the above stated function will be described with reference to FIG. 2. FIG. 2 is a schematic block diagram showing the structure of a conventional plesiochronous matching apparatus. In the matching apparatus in FIG. 2, there is shown a case where a frame cycle is used as a slip unit for slip control.
Referring to FIG. 2, a plesiochronous matching apparatus has a structure in which first equipment and a second equipment are provided symmetrically with respect to a synchronizing control circuit 50 at the center of the Figure. The on-line equipment operates in the normal state, while the non-on-line equipment is a complementary equipment of the on-line equipment and operates in case of trouble and the like of the on-line equipment. In the following, the explanation is made with respect to an example in which the equipment represented by a suffix "a" acts as the on-line equipment and the equipment represented by a suffix "b" acts as the non-on-line equipment. Although those equipments represented by the suffixes "a" and "b" may operate in the reversed manner, the explanation of such a case is omitted because the operations of the reversed equipments is completely symmetrical to the following.
In the figure, the small letter a is attached to the on-line equipment and the signals related thereto and the small letter b is attached to the non-on-line equipment and the signals related thereto.
In FIG. 2, 10 indicates a data input terminal of a plesiochronous matching apparatus; 11 indicates an entered data signal; 12a and 12b indicate clock extracting circuits; 13a and 13b indicate extracted clock signals; 14a and 14b indicate frame extracting circuits; 15a and 15b indicate extracted frame signals; 16a and 16b indicate write address counters; 17a and 17b indicate write address signals; 18a and 18b indicate write address counter synchronizing output signals; 19a and 19b indicate write address counter external synchronizing input signals; 20a and 20b indicate matching buffer memory circuits; 21a and 21b indicate buffer control circuits; 22a and 22b indicate memory control signals; 30a and 30b indicate buffer memory read data signals; 31a and 31b indicate read address counters; 32a and 32b indicate read address signals; 33a and 33b indicate read address counter control signals; 34a and 34b indicate read address counter control input signals; 35a and 35b indicate read address counter synchronizing output signals; 36a and 36b indicate read address counter external synchronizing input signals; 40 indicates a switching circuit; 41 indicates an output data signal; 42 indicates a data output terminal of the plesiochronous matching apparatus; 43 indicates a clock signal input terminal on the read side; 44 indicates a clock signal on the read side; 45 indicates a frame signal input terminal on the read side; 46 indicates a frame signal on the read side; 50 indicates a synchronizing control circuit; 51 indicates a selection signal input terminal; 52 indicates a selection signal.
In the following, the operation of the circuit shown in FIG. 2 will be described. Although the following description is given particularly to the on-line equipment indicated with the small letter a, the non-on-line equipment indicated with the small letter b operates fundamentally in the same manner as in the on-line equipment and, therefore, the description thereof is omitted.
The input data signal 11 entered through the data input terminal 10 of the plesiochronous matching apparatus is applied to the clock extracting circuit 12a, the frame extracting circuit 14a and the matching buffer memory circuit 20a. The clock extracting circuit 12a extracts a clock signal from the input data signal 11 and applies the extracted write clock signal 13a to the frame extracting circuit 14a and the write address counter 16a. The frame extracting circuit 14a extracts a write frame timing signal based on the input data signal 11 and the write clock signal 13a and applies the extracted write frame timing signal 15a to the write address counter 16a. The write address counter 16a provides the write address signal 17a and the write address counter synchronizing output signal 18a based on the extracted write clock signal 13a and the extracted write frame signal 15a. The write address counter 16a operates periodically with a cycle longer than write frame cycle corresponding to the capacity of a plesiochronous buffer which, as mentioned before, usually corresponds to an integer multiple of the frame capacity. The parallel write address signal 17a consists of signal components having cycles longer than the write frame cycle and signal components having cycles equal to or shorter than the write frame cycle. The latter components always operate in synchronism with extracted write frame signal 15a. The write counter synchronizing output signal 18a, which has the above stated longest cycle, is provided according to the timing with which the write address counter 16a resets the output thereof. The write address counter external synchronizing input signal 19a provided from the synchronizing control circuit 50 is a signal for controlling the write address counter 16a and if this signal 19a is applied, the parallel output components of the write address counter 16a having longer cycles than the frame are forcedly reset irrespective of the amount of the output. The input data signal 11 applied to the matching buffer memory circuit 20a is written into the memory circuit 20a according to the write address signal 17a.
The read address counter 31a performs counting operation based on the read clock signal 44 applied from the read clock signal input terminal 43 and the read frame timing signal 46 applied from the read frame signal input terminal 45. The read address counter 31a provides the read address signal 32a to the matching buffer memory circuit 20a and the buffer control circuit 21a. This parallel read address signal 32a also contains signal component having cycles equal or shorter than the read frame cycle so as to perform the operation synchronizing with the read frame timing signal 46 and signal components having cycles longer than read frame cycle in the same manner as in the case of the write address signal 17a. The read address counter 31a provides the read counter synchronizing output signal 35a to the synchronizing control circuit 50 with the timing for resetting the output of the counter 31a, while parallel output components of the counter 31a having longer cycles than read frame cycle are forcedly reset by the read address counter external synchronizing input signal 34a applied from the synchronizing control circuit 50. Further, the read address counter 31a performs, in addition to the normal periodical counting operation, discontinuous increment or decrement operation with steps equivalent to the number of addresses related to the data for one frame, according to the instruction of the read address counter control input signal 34a.
The buffer control circuit 21a detects a relative address difference between the write address signal 17a and the read address signal 32a and when the difference of the addresses exceeds a predetermined threshold value, the buffer control circuit 21a applies to the synchronizing control circuit 50, the read address counter control signal 33a according to the relative approaching state. This read address counter control signal 33a indicates a discontinuous advance in the addresses for one frame when the write address comes up with the read address. On the contrary, when the read address comes up with the write address, the read address counter control signal 33a indicates a discontinuous return in the addresses for one frame. In addition, the buffer control circuit 21a applies the memory control signal 22a to the matching buffer memory 20a. The matching control signal 22a serves to control the matching buffer memory 20a, so that write operation of the input data signal 11 based on the write address signal 17a and read operation of the buffer memory read data signal 30a based on the read address signal 32a are performed without interference with each other.
The switching circuit 40 operates according to the selection signal 52 applied from the selection signal input terminal 51 so as to select the output of the first equipment or the output of the second equipment as the output of on-line equipment. More specifically, it selects the buffer memory read data signal 30a from the matching buffer memory 20a constituting the on-line equipment so that the selected buffer memory read data signal 30a is provided to the data output terminal 42 as the output data signal 41 of the plesiochronous matching apparatus. In the case where the second equipment with the reference character "b" is set to be on-line, the selected buffer memory read data signal 30b is provided to the data output terminal 42 instead of signal 30a.
The synchronizing control circuit 50 controls selectively either the on-line equipment or the non-on-line equipment in synchronism according to the selection signal 52 in the same manner as in the switching circuit 40 and applies from the on-line equipment the synchronizing signals as an external synchronizing signal to the non-on-line equipment and to the on-line equipment itself. In case where the first equipment with reference character "a" is selected the on-line equipment, the address counter control signal 33a applied from the on-line buffer control circuit 21a is selected and this signal is applied as the read address counter control input signals 34a and 34b to both of the on-line read address counter 31a and the non-on-line read address counter 31b. Consequently, the on-line read address counter 31a and the non-on-line read address counter 31b both operate under the control of the on-line buffer control circuit 21a. Further, the synchronizing output signal 18a from the on-line write address counter 16a and the synchronizing output signal 35a from the read address counter 31a are selected respectively. These synchronizing output signals 18a and 35a are applied to the corresponding non-on-line counters 16b and 31b as the external synchronizing input signals 19b and 36b, respectively. Thus, non-on-line write address counter 16b and the non-on-line read address counter 31b operate in synchronism with the corresponding on-line address counters 16a and 31a, respectively.
As described above, the plesiochronous matching apparatus includes the on-line equipment and the non-on-line equipment. The above stated conventional apparatus is connected so that the non-on-line write address counter 16b and the non-on-line read address counter 31b perform counting operation under the control of the on-line write address counter 16a and the on-line read address counter 31a, respectively, in synchronism with the write and read counters of the on-line equipment. As a result, if a trouble, such as in existence of the plesiochronous slip control to be performed, occurs in the on-line write address counter 16a or read address counter 31a to bring it into a malfunction state, the corresponding non-on-line counter synchronizing with the counter in trouble is also brought into the malfunction state. Accordingly, the conventional plesiochronous matching apparatus has a disadvantage that if the non-on-line equipment (standby state equipment) is selected after detection of a trouble in the on-line equipment, the same data trouble as in the on-line equipment exists in the newly selected on-line equipment which has been a standby (non-on-line) equipment before the switching transition. Another disadvantage is that if troubles are detected simultaneously in both of the on-line and non-on-line equipment, the plesiochronous matching apparatus is brought into an inoperable state since the on-line and non-on-line equipment operate in synchronism.